1. Field of Invention
This invention relates to an apparatus and methods for increasing memory ultililzation, and more particularly to an apparatus and methods for increasing memory ultilization using a program ROM in a reduced instruction set computer (RISC) type of microprocessor to obtain an optimal memory utilization, without the necessity of changing the microprocessor architecture or modifying the instruction set.
2. Description of Related Art
In general, architectural design for the central processing unit (CPU) can be classified into two main types, namely, a Von Neumann architecture or a Harvard architecture. FIG. 1 shows a block diagram of the Von Neumann architecture and FIG. 2 shows a block diagram of the Harvard architecture. Referring to FIG. 1, in the Von Neumann architecture the central processing unit 100a puts both the program and data into the same memory 100b. Referring to FIG. 2, in the Harvard architecture the central processing unit 200a puts the program and data into two separate memories 200b and 200c, respectively. This permits central processing unit 200a to access the program and the data in parallel and enhance system efficiency.
FIG. 3 shows a block diagram of the microprocessor system UM6610 fabricated by United Microelectronics Corporation (UMC). The UM6610 is a 4-bit Harvard type CPU having an independent program bus ROMAD[0:F] and two data buses RAMA[0:9] and RAMD[0:3], respectively. The program bus is 16-bit and the data buses are 4-bit each. Program bus ROMAD [0:F] is address bus and data bus in time-sharing scheme.
Because a CPU having a Von Neumann architecture does not differentiate between memory usage such as program or data, whenever a large amount of supplementary data such as speech data is needed, all necessary is to divide up a memory space into separate areas using different RAM or ROM as demanded. For example, the memory locations for the program and speech data are planned beforehand and stored in a mask ROM. However, because a CPU having a Harvard architecture requires separating mask ROMs to store speech data and programs, it causes more expensive to make the integrated circuit (IC). Each ROM unit must necessarily have an independent decoder, and also can not share the same sense amplifier. Furthermore, each ROM unit requires a respective test, it causes a built-in testing procedure more complex. Moreover, for a low cost microprocessor such as a UM6610, the memory space of its data RAM is small, and is not suitable for applications requiring the mass storage of data such as speech data.
For example, a speech IC such as a UM5220 comprising an UM6610 microprocessor has the program and speech data installed in separate mask ROMs. As mentioned above, this will increase the manufacturing cost and make the testing procedures more complex. However, if the program ROM is replaced with the speech ROM, the problem of memory under-utilization will be serious for a microprocessor employing a UM6610 type of architecture.
FIG. 4 shows the operation of a RTNW (i.e., return word) instruction, FIG. 5 shows the operation of a TJMP (i.e., table jump) instruction and FIG. 6 shows how memory is wasted when a RTNW instruction is executed for retrieving speech data. Referring to FIGS. 4-6, the use of a RTNW instruction to retrieve an 8-bit data from the program ROM for a UM6610 microprocessor is actually having a memory utilization rate of 50%, because an instruction occupies 16 bits. As shown in FIG. 6, when the method according to the RTNW instruction is used, the high byte 600a in the data area 600 is the repeated RTNW op code, and only the low byte 600b in the data area 600 is the useful 8-bit data. This kind of arrangement implies memory wastage and is unacceptable for applications requiring a lot of data (such as speech synthesis).